1. Field of the Invention
The present invention relates to a data processing device and a data processing method, in particular, a data processing device and a data processing method in which a logic circuit is dynamically reconfigurable.
2. Description of the Related Art
In recent years, regarding a circuit for performing various data processings, a “dynamic reconfigurable logic device (dynamic reconfigurable hardware)” capable of dynamically changing a configuration of the circuit and dynamically changing a connection to a computing unit has been realized. Examples of the reconfigurable logic device include FPGA (Field Programmable Gate Array), CPLD (Complex Programmable Logic Device), PCA (Plastic Cell Architecture) and Reconfigurable Processor (RP). Such a reconfigurable logic device is regarded as a promising device capable of introducing flexibility of software into hardware having a characteristic of high-speed processing. Thus, apparatuses using this device have been proposed.
Japanese Laid-Open Patent Application JP-P2004-343559A discloses an example of a data processing device having a conventional reconfigurable integrated circuit unit. The data processing device has an integrated circuit unit capable of executing a plurality of data processings by changing at least a part of the circuit configuration. The data processing device further has a database which stores a plurality of configuration data available in the integrated circuit unit and a control unit which can select processing to be executed in the data processing device. The control unit has a reconfiguration function and a trial function. On the basis of the configuration data of the database, the reconfiguration function configures the integrated circuit unit so as to correspond to processing active in the data processing device. The trial function temporarily changes at least a part of the configuration of the integrated circuit unit on the basis of the configuration data of the database so that evaluation may be made when another processing which can be replaced with the active processing is performed in the data processing device, performs at least a part of the another processing on a trial basis and makes the highly-evaluated another processing the active processing in the data processing device. In this conventional example, a software wireless terminal using a reconfigurable processor (RP) is used. This example discloses a method of changing circuit configuration according to change in environment (communication quality in this example) by using a reconfigurable processor.
Japanese Laid-Open Patent Application JP-P2002-530780A (WO00/31652) discloses an example of a conventional reconfigurable programmable logic device computer system. The reconfigurable computer system has a central processing unit and a programmable logic. The central processing unit is run on at least one programmable logic device. The programmable logic is combined with the central processing unit and can be reconfigured so that performances of the computer system may be optimized to process a given application. This conventional example is an example of a reconfigurable computer using a programmable logic device (PLD). In this example, functions of an application run in the computer are allocated to a hardware processing part and a software processing part under constraint of hardware resource at the time of system design, and hardware resource allocation and software processing allocation are respectively performed at activation of the system.
International Publication WO01/090887 discloses a program processing method of performing a high-speed processing by using a conventional dynamic reconfigurable hardware and a program of executing the processing method. This program processing method is a processing method of a source program run on a computer. The program processing method has an evaluating step of analyzing a source program to obtain a use cost value of the computer resources in the unit of predetermined program modules forming the source program and selecting a program module with a high use cost value; an editing step of generating a hardware module object which constructs configuration of a dynamic reconfigurable hardware so as to perform processing of the selected program module, and adding a pseudo function of calling the selected program module to change the source program; an executing step of executing the changed source program by the hardware constructed according to the hardware module object and the computer. In this conventional example, the hardware module object using hardware which can dynamically reconfigure the program module with a high use cost value of computer resources is called at the time of edition of the software run on a CPU (Central Processing Unit).
In recent years, in the data processing devices, with an increase in an input/output line speed, an input/output traffic volume of the devices has increased. For this reason, to improve data processing performance, the number of parts where input/output data is processed by using hardware has increased. On the other hand, devices such as firewalls, intrusion detection/prevention devices, computer virus detectors and application layer relay devices, which deal with a higher-order network layer in terms of contents of data processing, are now in increasing demand. In such data processing devices, flexibility is required to address various protocols and applications. Thus, such tasks are mainly processed by software. However, a processing performance of software greatly depends on processing performance of a processor. Thus, to greatly improve a processing performance, it is necessary to execute “hardware offload” by separating off the processing to be hardware while sacrificing flexibility of the software.
In terms of offload, there are a software module, which performs processing on the CPU, and a hardware module, which performs processing in a hardware circuit in a processing block in the device. Generally, different processings are allocated to the software module and the hardware module, respectively. On the other hand, the same processing may be allocated to the software module and the hardware module. In this case, an application programming interface (API) of the software module and the hardware module can be defined so that the same result may be output when the same input data and parameter are given.
Since the hardware module is composed of a fixed hardware circuit, the hardware module has no flexibility in arrangement, such as whether to dispose the function on the device or in change of function. However, when a reconfigurable logic device is used in the device, it is possible to introduce the flexibility of software, in addition to a high-speed processing, into the hardware module. Unless specifically defined, hereinafter, the hardware module will be regarded as the hardware module expanded on the reconfigurable logic device.
In terms of the processing performance such as data processing volume per unit time and time necessary for data processing, the hardware module is more advantageous than the software module. On the other hand, resources necessary for a software processing are the CPU and a processing memory, and a resource necessary for the hardware processing is a logic element (reconfigurable or fixed). Consequently, in terms of resource costs, the hardware module is more expensive than the software module. The hardware module using a reconfigurable logic element is more expensive than the hardware module using a fixed logic element as a whole. Therefore, by setting the module with high frequency of use or the module with extremely excellent processing performance as the hardware module and the module with low frequency of use or the module having less difference in performance between the hardware and the software as the software module, cost performance of the whole device can be improved.
However, selection of the hardware module or the software module may vary depending on time zone, location of the device and so on. Variation due to time zone means the case where tendency of the data types varies with time. In this case, an environmental adaptation system using dynamic reconfiguration is especially effective in exhibiting performances. Conventionally, to address change in time and difference of location of the device, the function module has no option but to be the software module. However, by using the reconfigurable logic device, it becomes possible to address change in time and difference of location of the device also in the hardware module. Since the function can be changed in the same hardware at this time, the change of function can be achieved in the state where the processing performance is kept high.
When the reconfigurable logic device is used in the data processing device in this manner, the processing performance can be improved and the problem of flexibility of processing can be solved. However, in the data processing device using the existent reconfigurable logic device, there is no method of achieving various processings in the software module and the hardware module simultaneously, and switching processing between the software module and the hardware module.
For example, in the conventional technique disclosed in Japanese Laid Open Patent Application JP-P2004-343559A, it is presumed that processing circuit is used in which the processing scale is as small as that can be treated by the reconfigurable processor. That is, it is not assumed that processing is performed by software and the technique of dynamically switching between the software module and the hardware module is not disclosed. In the conventional technique disclosed in Japan Laid Open patent Application JP-P2002-530780A (WO00/31652), reconfiguration is carried out only at activation of the system and the technique of changing processing allocation between the hardware and the software during operation of the system is not disclosed. In the conventional technique disclosed in International Publication WO01/090887, the module processed by hardware is fixed at edition of the software and the technique of changing processing allocation between the hardware and the software during operation of the system is not disclosed.
As a related technique, Japanese Laid Open Patent Application JP-P2004-5110A discloses information equipment and a launcher program. The information equipment has a launcher function and includes an application activation judging means, a registered application search means and an application registering means. The application activation judging means judges that an application is activated from a function other than the launcher function. The registered application search means determines whether or not the application judged as being activated by the application activation judging means is registered in the launcher function. When determination is made that the application is not registered in the launcher function by the registered application search means, the application registering means registers the application in the launcher function.
Japanese Laid Open Patent Application JP-P2004-362446A discloses a calculator and a calculating method. The calculator has a hardware module, a storage unit and an execution unit. The hardware module performs a predetermined processing. The storage unit stores a software module which performs the same processing as the predetermined processing performed by the hardware module therein. The execution unit selects execution by the hardware module or execution by the software module stored in the storage unit. The hardware module is made to perform the processing when the execution by the hardware module is selected, and the software module is made to perform the processing when the execution by the software module is selected.